1. Field of the Invention
This invention relates generally to telecommunications, and more particularly, to wireless communications.
2. Description of the Related Art
Wide frequency tuning phase lock loop (PLL) systems may be used for a variety of mobile communication systems, including a global system for mobile communications (GSM), a universal mobile telecommunications system (UMTS), a wideband code division multiple access (WCDMA), a CDMA2000, a wide local area network (WLAN, and the like. For example, reconfigurable frequency generation PLL systems and wide tuning PLL systems may be deployed within terminals or handsets, such as mobile stations or base stations of such systems.
A phase-lock loop (PLL) is a device that generates a periodic output signal that has a constant phase and frequency relationship with respect to a periodic input signal. Many electronic systems use internal clocks that are required to be phase aligned to and/or frequency multiples of some external reference clock. For example, a reference clock is applied to an integrated circuit chip to drive a PLL, which then drives the system's clock distribution. The primary function of the PLL is to compare the distributed clock to the incoming reference clock, and vary the phase and frequency of its output until the reference and feedback clocks are substantially phase and frequency matched.
In a wide frequency tuning PLL system, a complete desired frequency span is separated into sub-ranges. However, all frequency spans of those sub-ranges normally overlap each other considerably, but due to tolerance issues, those predefined (designed-in) frequency sub-ranges may be changed during a lifetime of the system because of a host of factors, such as temperature and aging. There is no quality information about the actual design centering of those systems running in the field. In fast frequency hopping systems, a settling time and a phase-noise are two conflicting requirements such that both cannot be optimized at the same time. Therefore, any compromise between “speed” and “noise” leads to non-optimal solutions.
In wide tuning and/or fast hopping systems, a frequency span is subdivided into several sub-ranges. For each range, a special separate tuning element is included. This tuning element is switched on/off if required and an oscillator runs within the chosen sub-range. To this end, switching on/off capacitors or inductors may be accomplished by a switch matrix, which requires numerous radio frequency (RF) switches and/or tuning-elements placed “around” the oscillator. This architecture results in a poor oscillator design, leading to a significantly inferior performance. Alternatively, another well-known architecture utilizes a bank of oscillators, essentially meaning that the oscillator, which covers the actual tuning range will be switched “on,” which is relatively expensive to implement.
Accordingly, some shortcomings of the above mentioned solutions include a tolerance problem in the field, a complicated oscillator design with poor quality, no provision of a feedback and/or a quality test in the field, no provision for an update in the field, and lack of availability of information of the actual design centering in the field, causing a system to run “out of order.” If the system runs out of “range,” a base station may cease to function. As a consequence, an overall performance of a mobile network may be unacceptable because of many dropped calls. Other significant shortcomings of these solutions include a static and not adaptive system, parameters that are designed in and cannot be changed, inability to adapt to changes of the oscillator characteristic, a poor PLL settling time and a poor phase noise, a relatively large production spread without the possibility of self-alignment, and a requirement of an extreme wide tuning sub-ranges in order to cover all tolerance problems.
The present invention is directed to overcoming, or at least reducing, the effects of, one or more of the problems set forth above.